1. Field of the Invention
The present invention relates to a MOS dynamic semiconductor memory cell used in an insulating gate type dynamic random access memory or the like and a semiconductor memory including an array of the memory cells.
2. Description of the Related Art
A conventional MOS dynamic memory cell is shown in FIGS. 1 and 2. In FIGS. 1 and 2, one transfer gate MOS transistor (e.g., an n-channel type) T is connected in series with one capacitor element C. Reference numeral 81 denotes a p-type semiconductor substrate; 82, a gate oxide film; 83, a capacitor insulating film; 84, an element isolation region; 85 and 86, drain and source n-type impurity layers; 87, an n-type impurity layer for electric charge storage; 88, a capacitor electrode consisting of polysilicon; and G, a gate electrode consisting of polysilicon.
In the memory cell shown in FIGS. 1 and 2, the gate electrode G is connected to a word line WL, and the drain n-type impurity layer 85 is connected to a bit line BL. The semiconductor substrate 81 has a fixed potential common to that of each memory cell and, normally, has a power source potential Vss of the semiconductor memory or a negative potential generated in the semiconductor integrated memory. This fixed potential is not changed except when, e.g., noise adversely affects this potential.
As described above, an n-channel type MOS transistor having a fixed substrate potential serves an enhancement type MOS transistor. FIG. 3 shows a typical relationship between a threshold voltage Vth and a substrate potential Vbb of the enhancement type MOS transistor. Within a range of the substrate potential Vbb used in practice, Vth &gt;0 V. Therefore, in order to write data up to the limit level (normally, power source voltage Vcc) of the logical amplitude of the bit lines a voltage boosted (bootstrap) to (Vcc +Vth) or more must be applied to the word line and the MOS transistor must be turned on in a triode region to prevent a threshold voltage loss caused by this MOS transistor. In addition, when the bit line is high, the Vth value is higher than that when the bit line is low, because of the back-gate bias effect. The boosted level of the word line must exceed (Vcc +Vth) where the Vth value is defined when the bit line is high.
When the voltage of the word line is boosted, many problems in, e.g., the operation margin and reliability of the memory cell element are caused along with miniaturization of the memory cell element of the semiconductor memory. In addition, in order to boost the voltage of the word line, a large-sized word line booster having a complicated arrangement is required. Therefore, even if a CMOS circuit is arranged in the semiconductor memory to achieve a simple circuit, a sufficient operation margin, and high reliability, the performance and reliability of the semiconductor memory are considerably degraded due to the need of the boosted voltage of the word line, and an effect of the CMOS circuit is undesirably lost.